1. ​Run-time Reconfiguration

Our group is world-renowned for its pioneering work in run-time reconfigurable FPGA design. We have developed an automated tool flow to accomplish micro-reconfiguration (a fast method for reconfiguring small parts of the FPGA at run-time) tailored to implement a parametrized application. In this novel approach, the infrequently changing input values of a design - called its parameters - are implemented as constants and the design is optimized for these constants. When the input parameter values change, the design is re-optimized for the new constant values by reconfiguring the FPGA. This way, we use specialized (constant) calculation blocks (such as multipliers) instead of generic functions (multiplications) with bulky generic blocks that consume a substantial amount of FPGA resources. This can reduce the FPGA resource utilization and can thus improve the performance of the resulting design significantly. 

Staff: Dirk Stroobandt
Researchers: Vijaykumar Guddad
Projects: imec.icon project (cREAtIve)
Publications: Dirk Stroobandt

2. FPGA Compilation (High-level Synthesis, Placement and Routing)

Many of the old compilation techniques are designed for single-core processors. It is hard to adapt these old techniques in order to exploit the acceleration potential of the multiple cores in the modern workstations. We have investigated the main runtime consuming parts of the old techniques and proposed new compilation techniques that can accelerate these parts by exploiting the multi-core processor environment. We propose new pack, placement and routing techniques that improve the runtime and quality. These efforts contribute to a shorter FPGA design cycle and a smaller divide between the academic and commercial results. Our new compilation tools have been made available to the academic community in an open source project which is implemented in Java. 

Staff: Dirk Stroobandt
Researchers: Raveena Raikar, Yun Zhou
Projects: Gift from Xilinx for research on placement, Routing and industrial research project with Huawei, PhD grant of China Scholarship Council (CSC)
Publications: Dirk Stroobandt​

3. On-chip Interconnection Networks

Interconnection networks play a crucial role in the design of high performance parallel processing computing platforms. NoCs are generally subject to stringent, and often conflicting, timing, power, area, and reliability constraints due to the continuous integration scale. Moreover, with the aggressive scaling of the VLSI technology, NoCs are rapidly becoming so complex that designing them to rely on static configurations will be
prohibitively inefficient and insufficient. As a result, we focus on extending the design methodology of large-scale NoCs in order to develop systems which are able to continually adapt to changes and automatically orchestrate the network activities based on the underlying dynamic environment​.

Staff: Dirk Stroobandt

​EXTRA: Exploiting eXascale Technology with Reconfigurable Architectures (supported by the European Commission in the context of H2020 FETHPC2014 ​funding programme​, project no.  671653, 1/9/2015 - 31/8/2018) 

HELP Video!: A platform for embedded, efficient, low Latency, and portable video processing (​imec.icon research project funded by imec and Agentschap Innoveren & Ondernemen, 1/10/2016 - 30/9/2018) 

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration (supported by the European Commission in the context of FP7 funding programme, project no.  287804​, 1/9/2011 - 31/8/2015)

Home-MATE: Home-compatible Multimodal Alarm Triggering for Epilepsy (GOA (Geconcerteerde OnderzoeksActie) project funded by Ghent University, 1/1/2008 - 31/10/2015)

OptiMMA: Optimization of MP-SoC Middleware for Event-driven Applications (SBO (Strategic Basic Research) project funded by IWT, 1/1/2008 - 31/12/2011)

FlexWare: Exploitation of Flexible Hardware Platforms for Massively Parallel Bioinformatics Applications (IWT-sponsored SBO project, 1/1/2007 to 31/12/2010) 

Intelligent autonomous systems with built-in digital spiking neural network (FWO project, project no. G.0317.05, 1/1/2005-31/12/2008) 

Measuring and preventing side-channel information leakage in integrated circuits (FWO project, project no. G.0475.05, 1/1/2005-31/12/2008)

PICMOS: Photonic Interconnect Layer on CMOS by waferscale integration (EU FP6 IST (Information Society Technologies) STReP (Specific Targeted Research Project), project no. FP6-2002-IST-1-002131, 1/1/2004-31/12/2006)

RESUME: Reconfigurable Embedded Systems for Use in Scalable Multimedia Environments (IWT-sponsored GBOU project, 1/1/2003 to 31/12/2006) 

Reconfigurable hardware for embedded systems (FWO project, project no. G.0021.03, 1/1/2003-31/12/2006)

Interconnection-based design methodology for Systems-on-a-Chip (UGent-BOF VEO project, 1/2/2003-31/1/2005)

Embedded Systems for Multimedia Applications Toward an Efficient Design Methodology (UGent-BOF GOA project, 1/2/2003-31/1/2005)

IO: Interconnect by Optics (EU Research Framework Programme EU-RFP5, project no. 00.0539-2, 1/9/2001-1/8/2004)

Boraflex (IWT O&O project with Siemens & HoGent)